The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size (e.g., shrinking the semiconductor process node towards the sub-20 nm node), which allows more components to be integrated into a given area. As the demand for miniaturization, higher speed and greater bandwidth, as well as lower power consumption and latency has grown recently, there has grown a need for smaller and more creative techniques of manufacturing semiconductor dies.
However, as individual devices achieve smaller and smaller sizes, the ability to reduce the size even further comes up against larger and larger hurdles. As such, the ability to pack a larger and larger number of devices onto the same size footprint also comes up against larger and larger hurdles. As such, additional techniques and manufacturing processes need to be developed in order to continue the process of manufacturing more and more devices within a footprint of a semiconductor device.